In the semiconductor industry, there is a continuing trend toward higher device densities. To achieve these high densities, there has been and continues to be efforts towards scaling down device dimensions (e.g., at submicron levels) on semiconductor wafers. In order to accomplish such high device packing densities, smaller and smaller feature sizes are required in integrated circuits (ICs) fabricated on small rectangular portions of the wafer, commonly known as dies. These smaller features can include width and spacing of interconnecting lines, spacing and diameter of contact holes, surface geometry such as corners and edges of various features as well as surface geometry of other features. To scale down device dimensions, more precise control of fabrication processes is required. The dimensions of and between features can be referred to as critical dimensions (CDs). Reducing CDs and reproducing more accurate CDs facilitates achieving higher device densities through scaled down device dimensions and increased packing densities.
Semiconductor integrated circuits undergo a variety of processing steps during manufacture, such as masking, resist coating, etching, deposition, etc. In many of these steps, material is overlayed or removed from the existing layer(s) at specific locations in order to form desired elements of the integrated circuit. Proper alignment of the various process layers is important, as the shrinking dimensions of modern integrated circuits require increasingly stringent overlay alignment accuracy. If proper alignment tolerances are not achieved, device defects can result.
Some types of alignment systems and/or methods employ large global alignment marks to align the wafer. For such systems and/or methods, a reticle includes a design pattern and an alignment mark. The alignment mark is typically located outside of the design pattern, although the alignment mark could be located within the design region, but at the expense of sacrificing design area real estate. The design pattern and alignment mark can be printed at several predetermined fields of a wafer. These printed alignment marks are found by a stepper system and are employed in wafer alignment, for example, for subsequent processing. The alignment marks typically resemble grating patterns with structures extending in orthogonal x and y directions, thus enabling alignment in the x and y directions between the wafer and the reticle with respect to adjacent layers. In some instances, alignment marks are printed within each exposure field to facilitate more precise alignment between the reticle and the wafer. For instance, the global alignment marks can be utilized to coarsely align exposure fields with the reticle, and the smaller alignment marks can be employed to more precisely align the exposure fields and the reticle.
Conventionally, alignment marks are created on a wafer substrate prior to placing one or more layers on the wafer. Thus, if a wafer comprises twenty layers of circuit components, a reticle associated with the twentieth layer will be aligned to the wafer with the same alignment marks utilized by a reticle associated with the second layer. According to another commonly employed technique, alignment marks are created with each layer formed upon the semiconductor wafer, and a subsequently formed layer is aligned to the alignment mark on the layer formed immediately prior. If errors in alignment are repeated over a plurality of layers, a wafer will be scrapped and throughput efficiency will be negatively affected.